The high speed performance of a digital logic gate is commonly characterized using circuits such as ring oscillators, delay chains and the like. In these circuits, the time T for a signal to propagate through some number n of identical gates is measured and the delay per stage is typically determined as T/n. Such measurements, however, do not allow the independent measurement of pullup and pulldown performance, but instead yield an average of the pullup and pulldown delays associated with the logic gates. Furthermore, using conventional measurement methodologies, input and output slews are undesirably fixed by the condition that all gates drive and are driven by gates nominally identical to themselves. Each gate generally has a single input that is toggled, and that selection is hardwired in place at the time of layout.
In circuits fabricated using a partially depleted Silicon-On-Insulator (SOI) process, circuit delay is typically a function of switching history of the circuits. This switching history dependence can significantly complicate the design of such circuits. History is generally determined as a tradeoff among the effects of drain-to-body and source-to-body leakage currents (long time constants) and very rapid dynamic capacitive coupling effects. The presence of gate-to-body tunneling further complicates the device design.
Conventionally, experiments performed to evaluate history effects are generally delay chain experiments, in which steady state delays are measured and compared with delays for different input patterns. Such experiments, however, have not agreed particularly well with model predictions. One shortcoming of these traditional approaches is that they only allow a single specific switching pattern, such as, for example, all top-switching four-way NAND gates, or all bottom-switching four-way NAND gates. More complex switching patterns in which the order of logic gate input switching varies over time, are not possible using conventional methodologies.